The reference clock for the PLL can be from either of the following:
- An internal clock sourced by CIPS (HSM0 of the HBM SLR)
- Dedicated clock pins in the same IO bank as the HBM (800 and 801)
Based on the input clock frequency provided and the desired operation rate of the HBM, the dedicated PLL is automatically configured to match the requirements.
A Differential Clock Capable IO (CCIO) pin provides the reference clock of 100 MHz to 500 MHz from the external source to the PLL. There are two IO standards supported: LVCMOS and LVDS. The dedicated clock pair are C4CCIO_PAD0 and _PAD1. C4CCIO_PAD0 is the P-side and _PAD1 is the N-side of the LVDS differential pair. When using as single-ended, connect the clock to C4CCIO_PAD0 and configure as LVCMOS12.
Internal clock source (HSM0) has a range of 100-200 MHz and the external clock has a range of 100-500 MHz. Internal clocking is preferred for ease of use, as the HBM clock is sourced from the CIPS, eliminating the need for an externally routed reference clock. When you select this option, a single clock from the CIPS (HSM0 of the HBM SLR) is used as the reference clock for both HBM stacks. External clocking is supported for flexibility, allowing two independent clocks to be provided by the user, one for each stack. There are no frequency or phase dependencies between the two clocks.
Refer to the Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960) for information on supported data rates.