The NoC is clocked by a single clock for the entire chip. The NMUs/NSUs have asynchronous integrated (first in first outs) FIFOs to ensure transition from the AXI clock domain of an individual master or slave to the NoC clock domain.
The NoC clock is controlled by a PLL inside the CIPS Control, Interface, and Processing System (CIPS) IP. To Change the NoC Clock Frequency the CIPS IP must be opened and used. This can be done using a Tcl command or via the GUI as shown in the following figure.
For more details about the NPLL refer to the Clocks Chapter in the Versal Adaptive SoC Technical Reference Manual (AM011).
| Clock | Description |
|---|---|
| aclkn | The AXI NoC and AXIS NoC IP can be configured to have up to N independent AXI clocks, where N is the sum of the number of AXI interfaces on the IP core. Each AXI interface of the NoC is automatically associated with a clock. |
| sys_clk | If an instance of axi_noc is
configured to include an integrated DDRMC, one sys_clk port appears on the boundary of the IP for each DDRMC. This port
must be connected to a clock source whose frequency is user-selectable on the DDR
Basic tab of the AXI NoC configuration
dialog. The DDR Basic tab also allows selection from three available System Clock
options: Differential, No Buffer, or Internal. Both Differential and No Buffer require
a differential clock source that must be placed on a global clock (GC) input pin in
any of the three XPIO banks used by a DDRMC. Internal uses a clock generated on-chip
in the CIPS IP. This clock is used internally by the DDRMC to generate various clocks
for the controller and external DDR memory.The Internal System Clock option is further described in subsequent sections. For
information on sys_clk input termination and I/O standards, see AC Coupling
Recommendations in the
Versal
Adaptive SoC SelectIO Resources Architecture Manual (AM010). The
clock generator driving |