Clamshell topology saves the component area by placing them on both sides (top and bottom) of the board. This mimics the address mirroring concept of multi-rank DIMMs. Address mirroring improves the signal integrity of the address and control ports while also making PCB routing easier. Only DDR4 single-rank components support the clamshell topology. The Clamshell option is available on the DDR Memory tab of the NoC configuration GUI.
There are two categories of components: non-mirrored and mirrored. As the following figure shows, one additional chip select signal is added to the design for the mirrored components. The figure in this example shows two CK pairs in addition to two chip select signals. This is because the load on one CK pair is greater than nine die with five single-rank, x16 DDP devices. Greater than nine loads on a CK pair results in signal integrity issues. Refer to the Versal Adaptive SoC PCB Design User Guide (UG863) for details on PCB design guidelines.