There are 64 CAL_SEQ_STATUS registers which contain the calibration stage codes as well as the status of each calibration stage. Calibration starts with CAL_SEQ_STATUS_0. There are 64 registers allowing for a maximum of 64 stages, but in practice only a subset is used.
The CAL_POINTER register indicates the current status and stage of calibration. By the time the Hardware Manager refreshes these registers, it is likely that calibration is complete. Do not expect to see it change values. In the event of a calibration error, it points at the stage where the error occurred. In the event of an error during calibration, the Vivado Hardware Manager displays additional information regarding the reason for failure.
The following table shows the encoding of the CAL_SEQ_STATUS and CAL_POINTER register.
| Register Bits | Description |
|---|---|
| CAL_SEQ_STATUS [8..6] |
Stage Status 0: Stage enabled, but not yet started 1: Stage not yet started, but will be skipped (invalid or unnecessary due to lower frequency operation) 2: Reserved 3: Calibration in progress 4: Calibration stage is skipped 5: Reserved 6: Calibration stage completed successfully 7: Calibration stage failed |
| CAL_SEQ_STATUS [5..0] |
Stage encoding. The following list represents the encoding of the stages, but does not imply the same sequence is used for calibration. 0x00: F0_PHY_BISC 0x01: F0_MEM_INIT 0x02: F0_LPDDR4_CS_CA_TRAIN 0x03: F0_LPDDR4_CA_VREF_TRAIN 0x04: F0_LRDIMM_DB_MREP 0x05: F0_LRDIMM_DB_MRD_CYCLE 0x06: F0_LRDIMM_DB_MRD_CENTER 0x07: F0_LRDIMM_DB_DWL 0x08: F0_LRDIMM_DB_MWD_CYCLE 0x09: F0_LRDIMM_DB_MWD_CENTER 0x0a: F0_DQS_GATE_CAL 0x0b: F0_READ_DQ_CAL 0x0c: F0_WRITE_LEVELING 0x0d: F0_WRITE_DQ_DBI_CAL 0x0e: F0_WRITE_LATENCY_CAL 0x0f: F0_READ_DBI_CAL 0x10: F0_READ_DQ_VREF_CAL 0x11: F0_READ_DQ_DBI_CAL_COMPLEX 0x12: F0_WRITE_DQ_VREF_CAL 0x13: F0_WRITE_DQ_DBI_CAL_COMPLEX 0x1a: F0_PRBS_READ 0x1b: F0_PRBS_WRITE 0x1f: FREQ_SWITCH 0x20: F1_PHY_BISC 0x21: F1_MEM_INIT 0x22: F1_LPDDR4_CS_CA_TRAIN 0x23: F1_LPDDR4_CA_VREF_TRAIN 0x24: F1_LRDIMM_DB_MREP 0x25: F1_LRDIMM_DB_MRD_CYCLE 0x26: F1_LRDIMM_DB_MRD_CENTER 0x27: F1_LRDIMM_DB_DWL 0x28: F1_LRDIMM_DB_MWD_CYCLE 0x29: F1_LRDIMM_DB_MWD_CENTER 0x2a: F1_DQS_GATE_CAL 0x2b: F1_READ_DQ_CAL 0x2c: F1_WRITE_LEVELING 0x2d: F1_WRITE_DQ_DBI_CAL 0x2e: F1_WRITE_LATENCY_CAL 0x2f: F1_READ_DBI_CAL 0x30: F1_READ_DQ_VREF_CAL 0x31: F1_READ_DQ_DBI_CAL_COMPLEX 0x32: F1_WRITE_DQ_VREF_CAL 0x33: F1_WRITE_DQ_DBI_CAL_COMPLEX 0x3a: F1_PRBS_READ 0x3b: F1_PRBS_WRITE 0x3c: EN_VT_TRACK 0x3d: READ_DQS_TRACK 0x3e: LPDDR4_WRITE_DQS_OSC_TRACK 0x3f: CAL_DONE |
If calibration completes successfully, CAL_POINTER Status is b'110 (Calibration stage completed successfully) and the Stage is x3f (CAL_DONE). The concatenated value is x1bf. If calibration encounters an error, the Status is b'111 (Calibration stage failed) and the Stage indicates the failing stage.
If a calibration error occurs, Hardware Manager extracts the error code from the register CAL_ERROR. You can decode the error codes from Table 2.
If there is a bit or a nibble number given in the error message, it refers to the physical pin/nibble number given in the package file for the I/O triplet containing the memory controller.
There are three IO Banks in a triplet. The first IO bank contains nibbles 0..8, the next contains 9..17, and the last 18..26.
For example, if an error code for the memory controller in IO Banks 700/701/702 reported a failure in nibble 14. This corresponds with the fifth nibble in the second IO bank. The following is one of the pins in that nibble:
- IO_L17N_N5P5_M0P89_701
- N5 = Nibble 5 (0 to 8 in each IO Bank)
- P5 = Pin 5 (0 to 5 in each Nibble)
- M0 = Triplet 0 (0 to X in the adaptive SoC)
- P89 = Pin 89 (0 to 161 in each triplet )
- 701 = IO Bank 701