Addressing - Addressing - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

The NoC supports a rich set of addressing mechanisms. Every configured NMU and NSU in a design is assigned a unique 12-bit ID referred to as the destination ID (destID). When a packet arrives at an input port of a NoC packet switch (NPS), the following occurs:

  1. The NPS reads the packet’s destID and virtual channel number.
  2. It uses these values to look in the routing tables to find the output port to send the packet.

The output port determines the next segment of the route, delivering the packet to the next NPS or NMU/NSU.

You can configure an NMU in AXI4 mode to use one of four strategies to determine the destID. These strategies, in order of precedence, are as follows:

Fixed DestID
You can program a configuration register in the NMU to contain a single destination ID. When enabled, the programmed value specifies the destination for all memory mapped transactions originating from that NMU, regardless of address.
User-defined DestID
User logic in the PL region can drive the destination ID onto the destination interface pins of the NMU. This ID is then used to route the memory mapped transaction to the destination. Separate destination interface pins are provided for read and write transactions. The current release of Vivado does not support this feature.
Address remap
The NMU supports an address remapping mechanism to override the default address map, provide a programmed destination ID, and support simple address virtualization.
Address decode
The NMU can decode the physical address of the AXI transaction to determine the destination ID of the addressed resource. The NMU contains a set of address decoders and associated programmable registers. This allows you to map transactions that are destined for different regions of the physical address space to preprogrammed destIDs.