The Versal Memory Controller supports Address
and Command Parity for DDR4. If the DRAM detects a parity error, ALERT_n is driven low and detected by the memory controller. The
controller halts all traffic and attempts a re-try of the failed command. This requires
significant effort by the controller and physical interface (PHY) to recover and
re-try.
The PHY buffers need to be flushed, which can have a latency impact of several
microseconds. As a result, there is no guarantee of isochronous latency, and bandwith
requirements might not be met in this scenario. If an ALERT_n is detected during the retry attempt, the memory controller issues
a fatal interrupt. The DDRMC cannot recover from an ALERT_n event during retry. The system needs to reboot and memory content
is lost.