AMD Versal™ architecture and interconnect is consistent with the AMBA® AXI standard, and as such, each transaction is accompanied by an AXI ID. The master can use a single AXI ID for all its transactions, or it can issue different transactions with different IDs. The same AXI ID is returned with the transaction response. This means the master can use it to forward the response to the appropriate internal destination if there is more than one. An example of the use of the AXI ID within a complex master is an 8-channel DMA. Data transfers use eight different AXI IDs, one per channel. The descriptor access uses an additional eight AXI IDs, one per channel. By inspecting the AXI ID in the response, the DMA logic knows how to handle the arriving response.
An important aspect of AXI ID is that transactions which have the same AXI ID must be returned in the same order they were issued. Transactions with different IDs can be returned in any order. Suppose the master is a simple function with a single thread of data access. Using a single ID ensures that transactions return in the order they were issued. Using multiple IDs can cause transactions to be returned out of order.
This can require special handling in the master to understand the sequence, and possibly reorder the arriving responses. It might be preferable to use a single ID in such cases. However, in most cases better performance is achieved using multiple IDs. It is advisable to assess the possible performance improvement against the extra design complexity in the master.
One exception to this rule is transactions from an NMU to an NSU into PS or PL. At the NoC exit points into the PS and PL, the NSU only supports two bits of ID. The original AXI ID undergoes a simple form of ID compression down to two bits. This is equivalent to an outstanding ID limit of four. The limited number of outstanding IDs can limit the number of OT.
- All transactions use the same AXI ID for a maximum OT of 64. This is assuming a single master via NoC NMU).
- Each transaction uses a unique ID for a max OT of four.
These limits are independent for the read and write channels.