Figure 1. Connections for a 1x48 with ECC LPDDR4/4x Interface
The following figure shows the nibble utilization for a 1x48
interface (or 1x32 with ECC) in the non-flipped configuration. DQ indicates data
nibbles. AC indicates Address/Command/Control nibbles. sys_clk indicates a nibble comprising the System Clock pair, RESET_n,
and ALERT_n signals. Refer to Clocking for System Clock details.
Note: AC nibbles for the ECC device are on nibbles 0 and
1 in the third Bank. DQ nibbles for the ECC device are on nibbles 2 and 3 in the
third Bank and nibble 6 and 7 in the second Bank. For a 1x32 interface without ECC
all nibbles in the third Bank and nibbles 2, 3, 6, 7, and 8 in the second Bank are
free.
Important: The
nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble Utilization for 1x48 Component Interface
(Non-Flipped)
