Programming Sequence - 1.0 English - PG308

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

Document ID
PG308
Release Date
2025-08-12
Version
1.0 English

The following programming sequence sets up the I2S Transmitter:

  1. Setup the Channel MUX registers, if required.
    Note: It is not recommended to change this value at runtime.
  2. Program the SCLK Divider.
    Note: It is not recommended to change this value at runtime.
  3. Enable the core.

The following programming sequence sets up the I2S Receiver:

  1. Set up the Channel MUX registers, if required.
    Note: It is not recommended to change this value at runtime.
  2. Program the SCLK Divider.
    Note: It is not recommended to change this value at runtime.
  3. Program the AES registers to specify the 192 bits of Channel Status value.
  4. Enable the core and latch the AES Channel bit.
Note: After asserting either aud_mrst or m_axis_aresetn, the core needs to be disabled and enabled again.