Control Register (0x08) - 1.0 English - PG308

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)
Document ID
PG308
Release Date
2025-08-12
Version
1.0 English

This register lets you enable/disable the core.

Table 1. Receiver Control Register (0x08)
Bit Default Value Access Type Description
31:17 0 R Reserved
16 0 WO Latch AES Channel Status: Program this bit to latch the AES channel status bits from the registers. This latched value is then put onto the AXIS interface. This register is auto cleared.
15:4     Reserved
3 0x0 RO Selected 32-bit LR clock mode
2 0x0 R/W Valid when bit 1 is set. Selects left/right justification:
  • 0: Left justification
  • 1: Right justification
1 0x0 R/W Enable Left/Right Justification
0 0x0 R/W Enable: Setting this bit to ‘1’ enables the core operations. Setting this bit to ‘0’ disables the core operations.