The Parity Functionality figure shows the parity functionality of the core. When
enabled, parity is either generated on the out-bound wuser or
ruser signal or checked for errors against the in-bound data. The
parameters SI_PARITY and MI_PARITY determine whether the core acts as a parity endpoint
or whether it propagates parity information through while checking for errors.
AXI protocol does not define a dedicated parity signal to accompany its read
and write data channels. If parity protection is wanted, the AXI ruser and wuser signals
can transport one parity bit per byte of data. AXI masters can be designed to generate
parity for their wdata output, and detect parity
errors on their rdata inputs, based on parity bits
transported on their wuser or ruser ports. Similarly, AXI slaves can generate parity for rdata outputs and detect parity for wdata inputs. When designing with masters or slaves that
do not generate/detect parity on their own, the AXI Sideband Formatter
Utility IP
core can generate and detect parity on their behalf. By inserting
the AXI Sideband Formatter
Utility IP
core adjacent to the masters and/or
slaves, you can protect data transmissions across the interconnect topology, including
the various storage elements along the pathway.