Revision History - 3.1 English - PG300

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

Document ID
PG300
Release Date
2025-07-09
Version
3.1 English

The following table shows the revision history for this document.

Section Revision Summary
07/09/2025 Version 3.1
Features Updated section.
IP Facts Added Versal AI Edge Series (GTYP) support.
PHY Configuration and Status Updated register description.
Clocking Updated section.
Subsystem Configuration Screen Updated configuration options.
User Parameters Updated section.
Receive – Issues After Training Updated section.
12/11/2024 Version 3.1
Features Updated the section.
Table 1 Updated the table.
Audio AXI4-Stream Interface Added the table.
Register Space Updated the registers.
DSC and FEC Support Updated the section.
Subsystem Configuration Screen Updated the section.
Building the Example Design Updated the Vitis flow.
05/30/2024 Version 3.1
General updates Added AMD Artix™ -7 support.
05/18/2023 Version 3.1
General updates Made minor technical updates across the document.
05/04/2022 Version 3.0
General updates Made minor technical updates across the document.
11/10/2021 Version 3.0
Core Overview Added Artix UltraScale+ support.
Features Added DSC and HDCP feature.
FEC Interface

AXI4-Stream DSC Video Interface

AXI4-Stream PPS Receive Interface

Added ports.
User Parameters Added table.
06/30/2021 Version 3.0
Configuring HDCP Keys and Key Management Added EEPROM method for HDCP key management.
01/14/2021 Version 3.0
Core Overview Added line rate support for Versal devices.
HDCP 1.3 Registers Added new section.
HDCP 2.2/2.3 Registers Added new section.
Designing with the Subsystem
  • Added YUV420 support
  • Added DSC and FEC support
  • Added Adaptive Sync support
  • Added Versal device support
  • Added physical layout section
Versal Device Support Added note.
Programming Sequence Added bare-metal driver information.
AXI4-Stream Interface Color Mapping Added additional footnotes to table.
Example Design Added Versal device example design based on VCK190 platform.
Available Example Designs Added additional footnotes to table.
08/31/2020 Version 2.1
Core Overview Updated with device specific line rate information.
Designing with the Subsystem Added eDP support.
Example Design Added Configuring HDCP Keys and Key Management sections.
12/02/2019 Version 2.1
General updates
  • HDCP 2.2 support
  • FB Pass-through with HDCP 1.3 and HDCP 2.2
  • EDID I2C speed control added
  • Vitis flow updated in Chapter 6
  • Added Appendix E for Video EDID Helper Cores
05/22/2019 Version 2.1
Example Design MST FB Pass-through example design details added
12/05/2018 Version 2.0
HDCP Key Interface HDCP Ports added
DisplayPort MST Stream MST Ports added
Programming the Core in MST Mode MST Programming added
Pixel Mapping Examples on AXI4-Stream Interface (UG934-Compliant) UG934-compliant pixel mapping
04/04/2018 Version 1.0
Initial release. N/A