Register Space - 3.1 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)
Document ID
PG300
Release Date
2024-12-11
Version
3.1 English
This section lists the registers available in the DisplayPort 1.4 RX Subsystem The address map is split into the following regions:
  • DisplayPort RX IP
  • AXI IIC
  • HDCP Controller
  • AXI Timer
  • Clocking Wizard
  • Video EDID

The following table shows the address offsets of the helper cores.

Table 1. RX Subsystem Helper Core Address Offsets
Helper Core Address Space Address Offset
DisplayPort 8K 0x0000_0000
AXI IIC 4K 0x0000_2000
AXI Timer 4K 0x0000_3000
HDCP 1.x Subsystem 4K 0x0000_4000
Clocking Wizard 4K 0x0000_5000
HDCP 2.x Subsystem 16K 0x0000_8000
Video EDID 4K 0x0000_6000
The subsystem address propagation in the AMD Vivado™ IP integrator assigns the maximum addresses based on full-featured configuration. Ensure the following:
  1. Confirm that the DisplayPort 1.4 RX Subsystem IP is mapped to a base address where 16bits (lower significant bits) in the address are 0. For example, 0x44A00000 is correct, and 0x44A02000 causes errors.
  2. Ensure all 16 bits of the address range are reserved for the DisplayPort 1.4 RX Subsystem IP.