Receive – Training - Receive – Training - 3.1 English - PG300

This section contains debugging steps if the clock recovery or channel equalization is not happening at sink.

1. Try with a different source such as the DisplayPort Analyzer.
2. Change the cable and check again.
3. Put an AUX Analyzer in the Receive path and check if the various training stages match with those mentioned in DisplayPort Overview.
4. Probe the lnk_clk output and check the SI of the Clock is within the Phase Noise mask of the respective GT.
5. Check the RX Initialization Status register (0x0028) and PLL Lock Status (0x0018) register of the Video PHY Controller for Reset done and PLL lock for the active lanes.
6. Check the 0x43C and 0x440 registers for Symbol_Locked, Channel Equalization, and Clock Recovery Done.