The following table shows the correct mapping for all supported data formats.
| Format | BPC/BPP | R | G | B | Cr | Y | Cb | Cr/Cb | Y |
|---|---|---|---|---|---|---|---|---|---|
| RGB | 6/18 | [47:42] | [31:26] | [15:10] | – | – | – | – | – |
| RGB | 8/24 | [47:40] | [31:24] | [15:8] | – | – | – | – | – |
| RGB | 10/30 | [47:38] | [31:22] | [15:6] | – | – | – | – | – |
| RGB | 12/36 | [47:36] | [31:20] | [15:4] | – | – | – | – | – |
| RGB | 16/48 | [47:32] | [31:16] | [15:0] | – | – | – | – | – |
| YCrCb444 | 6/18 | – | – | – | [47:42] | [31:26] | [15:10] | – | – |
| YCrCb444 | 8/24 | – | – | – | [47:40] | [31:24] | [15:8] | – | – |
| YCrCb444 | 10/30 | – | – | – | [47:38] | [31:22] | [15:6] | – | – |
| YCrCb444 | 12/36 | – | – | – | [47:36] | [31:20] | [15:4] | – | – |
| YCrCb444 | 16/48 | – | – | – | [47:32] | [31:16] | [15:0] | – | – |
| YCrCb422 | 8/16 | – | – | – | – | – | – | [47:40] | [31:24] |
| YCrCb422 | 10/20 | – | – | – | – | – | – | [47:38] | [31:22] |
| YCrCb422 | 12/24 | – | – | – | – | – | – | [47:36] | [31:20] |
| YCrCb422 | 16/32 | – | – | – | – | – | – | [47:32] | [31:16] |
| YUV420 (even line) | 8/24 | – | – | – | – | [47:40] | [15:8] | – | [31:24] |
| YUV420 (odd line) | 8/24 | – | – | – | [15:8] | [47:40] | – | – | [31:24] |
| YUV420 (even line) | 10/30 | – | – | – | – | [47:38] | [15:6] | – | [31:22] |
| YUV420 (odd line) | 10/30 | – | – | – | [15:6] | [47:38] | – | – | [31:22] |
| YUV420 (even line) | 12/36 | – | – | – | – | [47:36] | [15:4] | – | [31:20] |
| YUV420 (odd line) | 12/36 | – | – | – | [15:4] | [47:36] | – | – | [31:20] |
| YUV420 (even line) | 16/48 | – | – | – | – | [47:32] | [15:0] | – | [31:16] |
| YUV420 (odd line) | 16/48 | – | – | – | [15:0] | [47:32] | – | – | [31:16] |
| YONLY | 8/8 | – | – | – | – | – | – | – | [47:40] |
| YONLY | 10/10 | – | – | – | – | – | – | – | [47:38] |
| YONLY | 12/12 | – | – | – | – | – | – | – | [47:36] |
| YONLY | 16/16 | – | – | – | – | – | – | – | [47:32] |
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The design allows the use of a faster pixel clock. For example, 150 MHz or higher video clock frequency for all standard video resolutions. DisplayPort 1.4 RX Subsystem Subsystem supports DMA mode without any internal line buffers for video display. You need to reproduce the exact video timing from the M_VID and N_VID values reported over MSA. The interface timing, in this case, is shown in the following figure.
Figure 1. RX Pixel Timing
Note: The
width of
rx_vid_vsync, rx_vid_hsync, rx_vid_enable, and the number of
hsync pulses shown in the previous figure above are scaled down to have better visibility.
The number of hsync pulses are equal to the number of active lines in a frame. The default
widths of rx_vid_hsync pulse is 16 and rx_vid_vsync pulse is 63. The widths hsync and vsync can be
controlled through software as per MSA.