Link is Trained - 3.1 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

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3.1 English

You can determine that the core is properly training by reading from the LANE_STATUS register and observing lane alignment and symbol lock on all active lanes. Additionally, it is advisable to ensure that the PLL is locked (per the Video PHY Controller) and reset is complete, which is also part of the PHY_STATUS register.