| Subsystem IP Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family 1 |
AMD Artix™ 7 (GTPE2) 4 AMD UltraScale+™ Families (GTHE4, GTYE4)AMD UltraScale™ Families (GTHE3) AMD Versal™ Adaptive SoCs (GTYE5, GTYP) |
| Supported User Interfaces | AXI4-Stream, AXI4-Lite, Native video |
| Resources | Performance and Resource Use web page |
| Provided with Subsystem | |
| Design Files | Hierarchical subsystem packaged with DisplayPort RX core and other IP cores |
| Example Design | AMD Vivado™ IP integrator |
| Test Bench | Not provided |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | Not provided |
| Supported S/W Driver | Standalone, Linux 2 |
| Tested Design Flows 3 | |
| Design Entry | Vivado Design Suite |
| Simulation | For supported simulators, refer to the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 70294 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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