Functional Operation - 3.1 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

Document ID
PG300
Release Date
2024-05-30
Version
3.1 English

At a system level, software copies the EDID of the connected sync device and writes it into the EDID byte array present within the Video EDID core through AXI4 Lite interface. EDID byte array size is 384 B. Video EDID receives I2C commands from DisplayPort RX Subsystem through AUX transactions and responds back with EDID data back to DisplayPort RX Subsystem based on the received request. EDID memory is split into segments and each segment is 128 B in size. All transactions will be based on the segment pointer within the EDID memory space. Refer to the VESA EEDC v1.2 specification or later for the protocol.