This interface is enabled when either FEC or DSC is selected.
| Port Name | I/O | Description |
|---|---|---|
| fec_rx_data_out[63:0] | I | FEC decoded data output from thr external FEC decoder and input to the subsystem, corresponding to all lanes. Lower significant 16-bits correspond to lane-0, and most significant 16-bits correspond to lane-3. |
| fec_rx_data_k_out[7:0] | I | Indicates whether the corresponding byte of fec_rx_data_out is a K-char. Bit[0] corresponds to fec_rx_data_out[7:0] and so on. |
| fec_rx_val_out | I | Qualifier for fec_rx_data_out and fec_rx_data_k_out signals. |
| fec_rx_ph_out[7:0] | I | Each bit indicates whether the corresponding byte in “fec_rx_data_out” is a FEC PH symbol. Bit[0] corresponds to fec_rx_data_out[7:0] and so on. |
| fec_rx_pm_out[7:0] | I | Each bit indicates whether the corresponding byte in fec_rx_data_out is a FEC PM symbol. Bit[0] corresponds to fec_rx_data_out[7:0] and so on. |
| fec_rx_clken | O | Clock enable to the external FEC decoder. |
| fec_rx_reset | O | Active-High reset to external FEC decoder. |
| fec_rx_valid_in[1:0] | O | Qualifier for the output data from the subsystem to external FEC decoder. Bit[0] corresponds to lane-0 and lane-1 and bit[1] corresponds to lane-2 and lane-3. |
| fec_rx_data_in[79:0] | O | Input 8b10b coded data to external FEC decoder and output from the subsystem. Lower significant 20-bits correspond to lane-0, and the most significant 20-bits correspond to lane-3. |
| fec_rx_enable_in | O | Enable signal to the external FEC decoder from the subsystem. |
| fec_rx_num_lanes[1:0] | O |
Number of lanes indication to the external FEC decoder.
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