DisplayPort Video PHY Main Link [Lane0–Lane3] - 3.1 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)
Document ID
PG300
Release Date
2024-12-11
Version
3.1 English
Table 1. DisplayPort Video PHY Main Link [Lane0–Lane3]
Port Name I/O Description
s_axis_lnk_rx_lane0_tdata[31:0] I Main link data for lane0
s_axis_lnk_rx_lane0_tvalid I Main link data valid for lane0
s_axis_lnk_rx_lane0_tready O Main link data ready for lane0
s_axis_lnk_rx_lane0_tuser[11:0] I Main link user data for lane0
s_axis_lnk_rx_lane1_tdata[31:0] I Main link data for lane1
s_axis_lnk_rx_lane1_tvalid I Main link data valid for lane1
s_axis_lnk_rx_lane1_tready O Main link data ready for lane1
s_axis_lnk_rx_lane1_tuser[11:0] I Main link user data for lane1
s_axis_lnk_rx_lane2_tdata[31:0] I Main link data for lane2
s_axis_lnk_rx_lane2_tvalid I Main link data valid for lane2
s_axis_lnk_rx_lane2_tready O Main link data ready for lane2
s_axis_lnk_rx_lane2_tuser[11:0] I Main link user data for lane2
s_axis_lnk_rx_lane3_tdata[31:0] I Main link data for lane3
s_axis_lnk_rx_lane3_tvalid I Main link data valid for lane3
s_axis_lnk_rx_lane3_tready O Main link data ready for lane3
s_axis_lnk_rx_lane3_tuser[11:0] I Main link user data for lane3