DisplayPort Registers - 3.1 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

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3.1 English

The DisplayPort Configuration Data is implemented as a set of distributed registers that can be read or written from the AXI4-Lite interface. These registers are considered to be synchronous to the AXI4-Lite domain and asynchronous to all others.

For parameters that might change while being read from the configuration space, two scenarios might exist:
  • In the case of single bits, either the new value or the old value is read as valid data.
  • In the case of multiple-bit fields, a lock bit might be used to prevent the status values from being updated while the read is occurring. For multi-bit configuration data, a toggle bit is used for indicating that the local values in the functional core should be updated.

Any bits not specified in the following tables are considered reserved and return 0 upon reading. The power on reset value of all the registers is 0 unless it is specified in the definition. Only address offsets are listed and the base addresses are configured by the AXI Interconnect.