| Offset | Access Type | Description |
|---|---|---|
| 0x05C | R/W | INTERRUPT_MASK_2. Masks the specified interrupt sources from
asserting the axi_init signal. When set 1, the specified interrupt
source is masked. This register resets to all 1s at power up. [31] - Adaptive-Sync SDP interrupt [30] - Adaptive-Sync vblank interrupt |
| 0x070 | R/W1C | [31] - Adaptive Sync SDP interrupt and generated when
Adaptive-Sync SDP packet is received [30] - Adaptive-Sync vblank interrupt and is generated when vblank value difference is detected between two consecutive frames |
| 0x2C0 | RO | [31:0] - Adaptive Sync SDP header |
| 0x2F0 | RO | [31:16] - Adaptive Sync Vertical Front Porch (VFP) derived based on Adaptive-Sync SDP reception. Assertion of Bit-31 of 0x070 has to read this register |
| 0x2F4 | RO | Assertion of Bit-30 of 0x070 must read this register 15:0
value. [15:0] - VBLANK of the incoming video stream [31:16] - VTOTAL of the incoming video stream |