Direct DPCD Register Access Through the APB Interface - Direct DPCD Register Access Through the APB Interface - 3.1 English - PG300

DisplayPort 1.4 RX Subsystem Product Guide (PG300)
Document_ID
PG300
Release_Date
2026-08-03
Version
3.1 English

The DisplayPort 1.4 RX Subsystem provides a direct DPCD access mode that allows the host processor to read and write DPCD register values through the APB interface, bypassing the normal AUX channel updates. This mode is enabled by setting bit [0] of APB offset 0x00B8 to 1.

Note: This mode is intended for PHY testing and debug. AMD does not support or verify direct alteration of DPCD registers during normal operation. Modifying these registers outside of the provided driver API can result in undefined behavior.
Table 1. DPCD Register Mapping Through Direct APB Access
APB Offset APB Bits Config Register DPCD Register DPCD Address Description
0x009C [4:0] kCFG_LINK_BW_SET kDPCD_LINK_BW_SET 0x00100 Link bandwidth:
  • 0x06 = 1.62G
  • 0x0A = 2.7G
  • 0x14 = 5.4G
  • 0x1E = 8.1G
0x00A0 [7] kCFG_LANE_COUNT_SET kDPCD_ENHANCED_FRAME_EN 0x00101[7] Enhanced framing enable
0x00A0 [6] kCFG_LANE_COUNT_SET kDPCD_TPS3_SUPPORT 0x00101[6] TPS3 support
0x00A0 [4:0] kCFG_LANE_COUNT_SET kDPCD_LANE_COUNT_SET 0x00101[4:0] Lane count (1, 2, or 4)
0x00A4 [7:6] kCFG_TRAINING_PATTERN_SET kDPCD_SYMBOL_ERROR_COUNT_SEL 0x00102[7:6] Symbol error count select
0x00A4 [5] kCFG_TRAINING_PATTERN_SET kDPCD_SCRAMBLING_DISABLE 0x00102[5] Scrambling disable
0x00A4 [4] kCFG_TRAINING_PATTERN_SET kDPCD_RECOVERED_CLOCK_OUT_EN 0x00102[4] Recovered clock output enable
0x00A4 [3:2] kCFG_TRAINING_PATTERN_SET kDPCD_LINK_QUAL_PATTERN_SET 0x00102[3:2] Link quality pattern set
0x00A4 [1:0] kCFG_TRAINING_PATTERN_SET kDPCD_TRAINING_PATTERN_SET 0x00102[1:0] Training pattern:
  • 0 = off
  • 1 = TPS1
  • 2 = TPS2
  • 3 = TPS3
0x00A8 [5:0] kCFG_TRAINING_LANE0_SET kDPCD_TRAINING_LANE0_SET 0x00103 Lane 0:
  • [1:0] = VS
  • [2] = VS max
  • [4:3] = PE
  • [5] = PE max
0x00AC [5:0] kCFG_TRAINING_LANE1_SET kDPCD_TRAINING_LANE1_SET 0x00104 Lane 1:
  • [1:0] = VS
  • [2] = VS max
  • [4:3] = PE
  • [5] = PE max
0x00B0 [5:0] kCFG_TRAINING_LANE2_SET kDPCD_TRAINING_LANE2_SET 0x00105 Lane 2:
  • [1:0] = VS
  • [2] = VS max
  • [4:3] = PE
  • [5] = PE max
0x00B4 [5:0] kCFG_TRAINING_LANE3_SET kDPCD_TRAINING_LANE3_SET 0x00106 Lane 3:
  • [1:0] = VS
  • [2] = VS max
  • [4:3] = PE
  • [5] = PE max
0x00C0 [2:0] kCFG_LINK_QUAL_LANE0_SET kDPCD_LINK_QUAL_LANE0_SET 0x0010B Link quality pattern lane 0
0x00C4 [2:0] kCFG_LINK_QUAL_LANE1_SET kDPCD_LINK_QUAL_LANE1_SET 0x0010C Link quality pattern lane 1
0x00C8 [2:0] kCFG_LINK_QUAL_LANE2_SET kDPCD_LINK_QUAL_LANE2_SET 0x0010D Link quality pattern lane 2
0x00CC [2:0] kCFG_LINK_QUAL_LANE3_SET kDPCD_LINK_QUAL_LANE3_SET 0x0010E Link quality pattern lane 3