The DisplayPort IP core supports CVT standard RB and RB2 reduced blanking resolutions. As per the CVT specifications, RB/RB2 resolution has HBLANK ≤ 20% HTOTAL, HBLANK = 80/160, and HRES % 8 = 0.
For the CVT standard, RB/RB2 resolutions end of the line
reset need to be disabled by setting the corresponding bit in the Line Reset Disable register
(offset address 0x0F0 for the TX). For the Non-CVT reduced blanking resolutions, where HRES is
non-multiple of 8, end of line reset is required to clear extra pixels in the video path for
each line.
The DisplayPort TX knows the resolution ahead of time and reset disable can be done during initialization. In the DisplayPort RX when the video mode change interrupt occurs, the MSA registers can be read to know whether the resolution is reduced blanking or standard resolution and the corresponding bit can be set.