FEC Interface - 3.1 English - PG299

DisplayPort 1.4 TX Subsystem Product Guide (PG299)

Document ID
PG299
Release Date
2024-12-11
Version
3.1 English

This interface is enabled when either “INCLUDE_FEC_PORTS” or “ENABLE_DSC” user parameter is enabled.

Table 1. DisplayPort 1.4 TX Subsystem FEC Interface
Port Name I/O Description
fec_tx_data_out[63:0] I FEC encoded data output from the external FEC decoder and input to the subsystem, corresponding to all lanes. Lower significant 16-bits correspond to lane-0 (2 consecutive link symbols from lane0), and most significant 16-bits correspond to lane-3.
fec_tx_data_k_out[7:0] I Indicates whether the corresponding byte of fec_tx_data_out is a K-char. Bit[0] corresponds to fec_tx_data_out[7:0] and so on.
fec_tx_val_out[7:0] I

Qualifier bits for fec_tx_data_out and fec_tx_data_k_out signals.

Bit[0] corresponds to fec_tx_data_out[7:0]

bit[1] corresponds to fec_tx_data_out[15:8] and so on.

fec_data_rd_ovr_out[7:0] I

When asserted, it indicates that the running disparity (RD) for the corresponding symbol on “fec_tx_data_out” should be forced to the value mentioned in corresponding bit of fec_data_rd_val_out during 8b/10b encoding of this data symbol in your transceiver.

Bit[0] corresponds to fec_tx_data_out[7:0],

Bit[1] corresponds to fec_tx_data_out[15:8] and so on.

fec_data_rd_val_out[7:0] I

When the bits in fec_data_rd_ovr_out are asserted, the running disparity for the corresponding symbol on fec_tx_data_out shall be forced to the value specified here in corresponding bit of “fec_data_rd_val_out.”

Bit[0] corresponds to fec_tx_data_out[7:0],

Bit[1] corresponds to fec_tx_data_out[15:8] and so on.

fec_tx_clken O Clock enable to the external FEC encoder
fec_tx_reset O Active-High reset to external FEC encoder.
fec_tx_num_lanes[1:0] O

Number of lanes indication to the external FEC encoder.

2’b00 – 1 lane

2’b01 – 2 lanes

2’b10 – 4 lanes

fec_tx_valid_in[1:0] O Qualifier for the output data from the subsystem to external FEC encoder. Bit[0] corresponds to lane-0 and lane-1 and bit[1] corresponds to lane-2 and lane-3.
fec_tx_data_ll_enc_in[7:0] O

Indicates that the FEC core is receiving LL codes for FEC encoding. When de-asserted, the corresponding symbol on “fec_tx_data_in” is not part of an RS(254,250) block and does not contribute to the parity calculation for the next block. This signal must remain de-asserted whenever the FEC encoding is disabled as well as during the arrival of FEC_PARITY_PH, FEC_PM, and FEC_DECODE_EN and FEC_DECODE_DIS sequences.

Bit[0] corresponds to fec_tx_data_in[7:0]

Bit[1] corresponds to fec_tx_data_in[15:8] and so on.

fec_tx_data_ph_in[7:0] O

When asserted, indicates that the corresponding symbol on fec_tx_data_in is a FEC_PARITY_PH symbol.

Bit[0] corresponds to fec_tx_data_in[7:0]

Bit[1] corresponds to fec_tx_data_in[15:8] and so on.

fec_tx_data_in[63:0] O Main link data to be encoded, from the subsystem to the external FEC encoder corresponding to all lanes. Lower significant 16-bits correspond to lane-0 (2 consecutive link symbols from lane0) and most significant 16-bits correspond to lane-3.
fec_tx_data_k_out[7:0] O

Indicates whether the corresponding byte of fec_tx_data_in is a K-char.

Bit[0] corresponds to fec_tx_data_in[7:0]

Bit[1] corresponds to fec_tx_data_in[15:8] and so on.