Timeout Prescaler Register - Timeout Prescaler Register - 1.2 English

Timeout Prescaler Register - Timeout Prescaler Register - 1.2 English - PG293

AXI Protocol Firewall IP LogiCORE IP Product Guide (PG293)

Document ID

PG293

Release Date

2025-08-29

Version

1.2 English

The Timeout Prescaler Register is shown in the following table. This functionality is not implemented when ENABLE_PRESCALER==0.

Table 1. Timeout Prescaler Register (0x230)
Bit(s)	Name	Core Access	Default Value	Description
31:16	Reserved	RW		Reserved
15:0		RW	0	Number of aclk cycles to wait before incrementing each of the MAX_WAITS timers. For each value n, each MAX_WAIT register (if enabled) prescribes a timeout period of MAX_WAIT * (n+1) aclk cycles.