Timeout Initial Delay Register - Timeout Initial Delay Register - 1.2 English

Timeout Initial Delay Register - Timeout Initial Delay Register - 1.2 English - PG293

AXI Protocol Firewall IP LogiCORE IP Product Guide (PG293)

Document ID

PG293

Release Date

2025-08-29

Version

1.2 English

The Timeout Initial Delay Register is shown in the following table. This functionality is not implemented when ENABLE_INITIAL_DELAY==0.

Table 1. Timeout Initial Delay Register (0x234)
Bit(s)	Name	Core Access	Default Value	Description
31:16	Reserved	RW		Reserved
15:0		RW	0	Number of MAX_WAIT timer cycles (after prescaling) to delay incrementing all MAX_WAITS timers after reset/power-on recovery. Following reset, incrementing of all MAX_WAITS timers is suppressed for TimeoutInitialDelay * (n+1) aclk cycles, where n is the Timeout Prescaler value.