SI-Side Interrupt Enable Register - SI-Side Interrupt Enable Register - 1.2 English - PG293

AXI Protocol Firewall IP LogiCORE IP Product Guide (PG293)

Document ID: PG293
Release Date: 2025-08-29
Version: 1.2 English

The SI-Side Interrupt Enable Register is shown in the following table.

Table 1. SI-Side Interrupt Enable Register (0x208)
Bit(s)	Name	Core Access	Default Value	Description
31		RW	0	Enable firewall blocking due to XILINX_WR_DECERR.¹
30		RW	0	Enable firewall blocking due to XILINX_WR_SLVERR.¹
29:28	Reserved	RW		Reserved
27		RW	0	Enable interrupt for User-defined Write Block.
26		RW	0	Enable interrupt for XILINX_WR_DECERR events.
25		RW	0	Enable interrupt for XILINX_WR_SLVERR events.
24:17		RW	0	Enable interrupt for corresponding fault in SI-side Fault Status Register Bits[24:17].
16	Reserved	RW		Reserved (Always zero)
15		RW	0	Enable firewall blocking due to XILINX_RD_DECERR.¹
14		RW	0	Enable firewall blocking due to XILINX_RD_SLVERR.¹
13:8	Reserved	RW		Reserved
7		RW	0	Enable interrupt for User-defined Read Block.
6		RW	0	Enable interrupt for XILINX_RD_DECERR events.
5		RW	0	Enable interrupt for XILINX_RD_SLVERR events.
4:1		RW	0	Enable interrupt for corresponding fault in SI-side Fault Status Register Bits[4:1].
0	Reserved	RW		Reserved (Always zero)
When any of Bits[31:30, 15:14] are disabled (0), the corresponding error response event can be recorded in the SI-side Fault Status Register and can still issue an interrupt if the corresponding "Enable interrupt" bit is set, but will not cause the firewall to become blocked.