The SI-Side Fault Status register is shown in the following table.
| Bit(s) | Name |
Core Access |
Default Value |
Description |
|---|---|---|---|---|
| 31:28 | Reserved | RO | All zeros | |
| 27 | User-defined Write Block | RO | 0 | This indicates a block resulting from writing and setting Bit[27] in the SI-Side Soft Fault Control Register. |
| 26 | XILINX_WR_DECERR | RO | 0 | |
| 25 | XILINX_WR_SLVERR | RO | 0 | |
| 24 | ERRM_WVALID_STABLE | RO | 0 | |
| 23 | ERRM_AWVALID_STABLE 1 | RO | 0 | |
| 22 | ERRM_AWADDR_BOUNDARY 1 | RO | 0 | |
| 21 | ERRM_WDATA_NUM | RO | 0 | |
| 20 | ERRM_AWSIZE 1 | RO | 0 | |
| 19 | RECM_WVALID_TO_AWVALID_MAX_WAIT | RO | 0 | |
| 18 | RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT | RO | 0 | |
| 17 | RECM_BREADY_MAX_WAIT | RO | 0 | |
| 16 | WRITE_RESPONSE_BUSY | RO | 0 | Indicates whether there are outstanding write transactions that still need to be completed on the MI; deasserts as soon as outstanding writes decrement to zero. (Not masked while writes are in normal operating mode.) |
| 15:8 | Reserved | RO | All zeros | |
| 7 | User-defined Read Block | RO | 0 | This indicates a block resulting from writing and setting Bit[7] in the SI-Side Soft Fault Control Register. |
| 6 | XILINX_RD_DECERR | RO | 0 | |
| 5 | XILINX_RD_SLVERR | RO | 0 | |
| 4 | ERRM_ARVALID_STABLE 1 | RO | 0 | |
| 3 | ERRM_ARADDR_BOUNDARY 1 | RO | 0 | |
| 2 | ERRM_ARSIZE 1 | RO | 0 | |
| 1 | RECM_RREADY_MAX_WAIT | RO | 0 | |
| 0 | READ_RESPONSE_BUSY | RO | 0 | Indicates whether there are outstanding read transactions that still need to be completed on the MI; deasserts as soon as outstanding reads decrements to zero. (Not masked while reads are in normal operating mode.) |
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