The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 08/29/2025 Version 1.2 | |
| Customizing and Generating the Core | Added a note on AXI Firewall used between two instances of SmartConnect. |
| 02/02/2022 Version 1.2 | |
| Features | Added optional independent control clock. |
| Timeout Faults | Updated timeout description. |
| MI-Side Mode Protocol Violation Faults | Updated the section. |
| User Parameters | Updated the section. Added ENABLE_CTL_CLOCK to ENABLE_INITIAL_DELAY rows. |
| Soft Pause Register | Added the section. |
| N/A | Added User-defined bits in register tables. |
| Clocking and Resets | Added conditional input pin aclk_ctl description. |
| Customizing and Generating the Core | Updated the figure. |
| 01/21/2021 Version 1.1 | |
| IP Facts | Updated the section. |
| Navigating Content by Design Process | Added the section. |
| Overview | Updated the section. |
| User Parameters | Updated the section. |
| Register Space | Updated the section. |
| General Design Guidelines | Updated the section. |
| Customizing and Generating the Core | Updated the section. |
| Upgrading | Updated the section. |
| N/A | Updated AR link. |
| 05/22/2019 Version 1.0 | |
| Introduction | Added DMA/Bridge Subsystem for PCIe. |
| 10/04/2017 Version 1.0 | |
| Initial release. | N/A |