The AXI Firewall IP requires one active-Low reset for all
interfaces, aresetn. The reset input is synchronous to aclk.
When ENABLE_CTL_CLOCK==1, the aresetn input is internally resynchronized to
the aclk_ctl clock to reset logic associated with the S_AXI_CTL interface.
AXI networks connected to the SI and MI interfaces should be reset concurrently with this
IP.