Port Descriptions - Port Descriptions - 1.2 English - PG293

AXI Protocol Firewall IP LogiCORE IP Product Guide (PG293)
Document ID
PG293
Release Date
2025-08-29
Version
1.2 English

The following table shows the AXI Firewall IP global signals.

Table 1. AXI Global Signals
Signals I/O Width Enablement Description
aclk I 1 Always

When ENABLE_CTL_CLOCK==0, aclk is the clock for all interfaces and all internal logic.

When ENABLE_CTL_CLOCK==1, aclk is the clock for the S_AXI and M_AXI interfaces, and the data pathway between them, including all checking, blocking and out-of-band error and interrupt signaling.
aclk_ctl I 1

ENABLE_CTL_

CLOCK==1

 Independent clock for the S_AXI_CTL interface and all control register writes and reads.
aclken I 1 Optional

Clock enable for all interfaces clocked by aclk. When ENABLE_CTL_CLOCK==0, aclken controls all interfaces.

When ENABLE_CTL_CLOCK==1, aclken controls only the S_AXI and M_AXI interfaces.
aresetn I 1 Always Active-Low reset for all interfaces (default tie-off = 1). When ENABLE_CTL_CLOCK==1, the aresetn input is internally resynchronized to reset logic associated with the S_AXI_CTL interface.

The following table shows the AXI Firewall IP Slave Interface signals.

Table 2. Slave Interface Signals
Signals I/O Default Width Description
s_axi_awid I

AXI3, AXI4: 0

AXI4-Lite: d/c

 ID_WIDTH Write Address Channel Transaction ID
s_axi_awaddr I REQ ADDR_WIDTH Write Address Channel Address
s_axi_awlen I

AXI3, AXI4: 0

AXI4-Lite: d/c

AXI4: 8

AXI3: 4

 Write Address Channel Burst Length (0–255)
s_axi_awsize I

AXI3, AXI4:

REQ

AXI4-Lite: d/c

 3 Write Address Channel Transfer Size Code (0–7)
s_axi_awburst I

AXI3, AXI4:

REQ

AXI4-Lite: d/c

 2 Write Address Channel Burst Type Code (0–2).
s_axi_awlock I

AXI3, AXI4: 0

AXI4-Lite: d/c

AXI4: 1

AXI3: 2

 Write Address Channel Atomic Access Type (0, 1)
s_axi_awcache I

AXI3, AXI4: 0

AXI4-Lite: d/c

 4 Write Address Channel Cache Characteristics
s_axi_awprot I 0b000 3 Write Address Channel Protection Bits
s_axi_awqos I

AXI4: 0

AXI4-Lite: d/c

 4 AXI4 Write Address Channel Quality of Service
s_axi_awregion I

AXI4: 0; AXI3,

AXI4-Lite: d/c

 4 AXI4 Write Address Channel Address Region Index
s_axi_awuser I

AXI3, AXI4: 0

AXI4-Lite: d/c

 AWUSER_WIDTH User-defined AW Channel Signals
s_axi_awvalid I REQ 1 Write Address Channel Valid
s_axi_awready O   1 Write Address Channel Ready
s_axi_wid I

AXI3: 0

AXI4,

AXI4-Lite: d/c

 ID_WIDTH Write Data Channel Transaction ID for AXI3 Masters
s_axi_wdata I REQ DATA_WIDTH Write Data Channel Data
s_axi_wstrb I all ones DATA_WIDTH/8 Write Data Channel Byte Strobes
s_axi_wlast I

AXI3, AXI4: 0

AXI4-Lite: d/c

 1 Write Data Channel Last Data Beat
s_axi_wuser I

AXI3, AXI4: 0

AXI4-Lite: d/c

 WUSER_WIDTH User-defined W Channel Signals
s_axi_wvalid I REQ 1 Write Data Channel Valid
s_axi_wready O   1 Write Data Channel Ready
s_axi_bid O   ID_WIDTH Write Response Channel Transaction ID
s_axi_bresp O   2 Write Response Channel Response Code (0–3)
s_axi_buser O   BUSER_WIDTH User-defined B Channel Signals
s_axi_bvalid O   1 Write Response Channel Valid
s_axi_bready I REQ 1 Write Response Channel Read
s_axi_arid I

AXI3, AXI4: 0

AXI4-Lite: d/c

 ID_WIDTH Read Address Channel Transaction ID
s_axi_araddr I REQ ADDR_WIDTH Read Address Channel Address
s_axi_arlen I

AXI3, AXI4: 0

AXI4-Lite: d/c

AXI4: 8

AXI3: 4

 Read Address Channel Burst Length code (0–255)
s_axi_arsize I

AXI3, AXI4:

REQ

AXI4-Lite: d/c

 3 Read Address Channel Transfer Size Code (0–7)
s_axi_arburst I

AXI3, AXI4:

REQ

AXI4-Lite: d/c

 2 Read Address Channel Burst Type (0–2)
s_axi_arlock I

AXI3, AXI4: 0

AXI4-Lite: d/c

AXI4: 1

AXI3: 2

 Read Address Channel Atomic Access Type (0, 1)
s_axi_arcache I

AXI3, AXI4: 0

AXI4-Lite: d/c

 4 Read Address Channel Cache Characteristics
s_axi_arprot I 0b000 3 Read Address Channel Protection Bits
s_axi_arregion I

AXI4: 0; AXI3,

AXI4-Lite: d/c

 4 AXI4 Read Address Channel address Region Index
s_axi_arqos I

AXI4: 0

AXI4-Lite: d/c

 4 AXI4 Read Address Channel Quality of Service
s_axi_aruser I

AXI3, AXI4: 0

AXI4-Lite: d/c

 ARUSER_WIDTH User-defined AR Channel Signals
s_axi_arvalid I REQ 1 Read Address Channel Valid
s_axi_arready O   1 Read Address Channel Ready
s_axi_rid O   ID_WIDTH Read Data Channel Transaction ID
s_axi_rdata O   DATA_WIDTH Read Data Channel Data
s_axi_rresp O   2 Read Data Channel Response Code (0–3)
s_axi_rlast O   1 Read Data Channel Last Data Beat
s_axi_ruser O   RUSER_WIDTH User-defined R Channel Signals
s_axi_rvalid O   1 Read Data Channel Valid
s_axi_rready I REQ 1 Read Data Channel Ready

The following table shows the AXI Firewall IP Master Interface signals.

Table 3. Master Interface Signals
Signals I/O Default Width Description
m_axi_awid O   ID_WIDTH Write Address Channel Transaction ID
m_axi_awaddr O   ADDR_WIDTH Write Address Channel Address
m_axi_awlen O  

AXI4: 8

AXI3: 4

 Write Address Channel Burst Length code. (0–255)
m_axi_awsize O   3 Write Address Channel Transfer Size code (0–7)
m_axi_awburst O   2 Write Address Channel Burst Type (0–2)
m_axi_awlock O  

AXI4: 1

AXI3: 2

 Write Address Channel Atomic Access Type (0, 1)
m_axi_awcache O   4 Write Address Channel Cache Characteristics
m_axi_awprot O   3 Write Address Channel Protection Bits
m_axi_awregion O   4 AXI4 Write Address Channel Address Region Index
m_axi_awqos O   4 Write Address Channel Quality of Service
m_axi_awuser O   AWUSER_WIDTH User-defined AW Channel Signals
m_axi_awvalid O   1 Write Address Channel Valid
m_axi_awready I REQ 1 Write Address Channel Ready
m_axi_wid O   ID_WIDTH Write Data Channel Transaction ID for AXI3 Slaves
m_axi_wdata O   DATA_WIDTH Write Data Channel Data
m_axi_wstrb O   DATA_WIDTH/8 Write Data Channel Data Byte Strobes
m_axi_wlast O   1 Write Data Channel Last Data Beat
m_axi_wuser O   WUSER_WIDTH User-defined W Channel Signals
m_axi_wvalid O   1 Write Data Channel Valid
m_axi_wready I REQ 1 Write Data Channel Ready
m_axi_bid I

AXI3, AXI4: REQ

AXI4-Lite: d/c

 ID_WIDTH Write Response Channel Transaction ID
m_axi_bresp I 0b00 2 Write Response Channel Response Code (0–3)
m_axi_buser I

AXI3, AXI4: 0

AXI4-Lite: d/c

 BUSER_WIDTH User-defined B Channel Signals
m_axi_bvalid I REQ 1 Write Response Channel Valid
m_axi_bready O   1 Write Response Channel Ready
m_axi_arid O   ID_WIDTH Read Address Channel Transaction ID
m_axi_araddr O   ADDR_WIDTH Read Address Channel Address
m_axi_arlen O  

AXI4: 8

AXI3: 4

 Read Address Channel Burst Length Code (0–255)
m_axi_arsize O   3 Read Address Channel Transfer Size Code (0–7)
m_axi_arburst O   2 Read Address Channel Burst Type (0–2)
m_axi_arlock O  

AXI4: 1

AXI3: 2

 Read Address Channel Atomic Access Type (0,1)
m_axi_arcache O   4 Read Address Channel Cache Characteristics
m_axi_arprot O   3 Read Address Channel Protection Bits
m_axi_arregion O   4 AXI4 Read Address Channel Address Region Index
m_axi_arqos O   4 AXI4 Read Address Channel Quality of Service
m_axi_aruser O   ARUSER_WIDTH User-defined AR Channel Signals
m_axi_arvalid O   1 Read Address Channel Valid
m_axi_arready I REQ 1 Read Address Channel Ready
m_axi_rid I

AXI3, AXI4: REQ

AXI4-Lite: d/c

 ID_WIDTH Read Data Channel Transaction ID
m_axi_rdata I REQ DATA_WIDTH Read Data Channel Data
m_axi_rresp I 0b00 2 Read Data Channel Response Code (0–3)
m_axi_rlast I

AXI3, AXI4: REQ

AXI4-Lite: d/c

 1 Read Data Channel Last Data Beat
m_axi_ruser I

AXI3, AXI4: 0

AXI4-Lite: d/c

 RUSER_WIDTH User-defined R Channel Signals
m_axi_rvalid I REQ 1 Read Data Channel Valid
m_axi_rready I   1 Read Data Channel Ready

The following table shows the AXI Firewall IP Control Register Interface signals.

Table 4. Control Register Interface Signals
Signals I/O Default Width Description
s_axi_ctl_awaddr I REQ 12 Write Address Channel Address
s_axi_ctl_awvalid I REQ 1 Write Address Channel Valid
s_axi_ctl_awready O   1 Write Address Channel Ready
s_axi_ctl_wdata I REQ 32 Write Data Channel Data
s_axi_ctl_wstrb I All ones 4 Write Data Channel Byte Strobes
s_axi_ctl_wvalid I REQ 1 Write Data Channel Valid
s_axi_ctl_wready O   1 Write Data Channel Ready
s_axi_ctl_bresp O   2 Write Response Channel Response Code (0–3)
s_axi_ctl_bvalid O   1 Write Response Channel Valid
s_axi_ctl_bready I REQ 1 Write Response Channel Ready
s_axi_ctl_araddr I REQ 12 Read Address Channel Address
s_axi_ctl_arvalid I REQ 1 Read Address Channel Valid
s_axi_ctl_arready O   1 Read Address Channel Ready
s_axi_ctl_rdata O   32 Read Data Channel Data
s_axi_ctl_rresp O   2 Read Data Channel Response Code (0–3)
s_axi_ctl_rvalid O   1 Read Data Channel Valid
s_axi_ctl_rready I REQ 1 Read Data Channel Ready

The following table shows the AXI Firewall IP Non-AXI signals.

Table 5. Non-AXI Signals
Signals I/O Width Enablement Description
mi_w_error O 1 Always Indicates MI-side firewall is blocked for writes due to a downstream write fault (sticky until unblocked).
mi_r_error O 1 Always Indicates MI-side firewall is blocked for reads due to a downstream read fault (sticky until unblocked).
si_w_error O 1 Always Indicates SI-side firewall is blocked for writes due to an upstream write fault (sticky until unblocked).
si_r_error O 1 Always Indicates SI-side firewall is blocked for reads due to an upstream read fault (sticky until unblocked).
ip2intc_irpt O 1 Always IRQ, as enabled by interrupt control registers.