The AXI Firewall IP internally records all outstanding
transactions, including ID thread and beat count. When the IP activates a block, all MI-side
forward-channel valid outputs are deasserted and no further commands are
issued on the MI.
m_axi_{ar,aw,w}valid without corresponding m_axi_*ready is an AXI protocol violation, however the affected channels of the
MI are assumed to be in an operationally invalid state when a block occurs, requiring a
downstream reset before returning to normal operation.Upon blocking, the IP also asserts
the MI-side response channel m_axi_{r,b}ready outputs for the duration of
the block.
Once blocked, the firewall autonomously issues
protocol-compliant response transfers on the SI for all outstanding (read or write)
transactions. Ordering among transaction responses per thread remains protocol-compliant, but
the ordering among multiple threads is non-deterministic. Read response transfers convey the
repeating rdata pattern 0xDEADFA11. All response transfers
indicate SLVERR response code.
Any further command transfers received on the SI during the block period are appended to the internal command queue and responded to in turn. That is, there is no requirement for upstream masters to promptly withhold subsequent commands after a block is triggered. However, no commands (or accompanying W-payload transfers) received prior to an unblock request get propagated to the MI.
The RESPONSE_BUSY bits in the MI-Side Fault Status Register indicate whether there are outstanding transactions that still
need to be completed on the SI. During all modes of operation, the BUSY bits assert as soon as
any activity associated with a new transaction are observed (arvalid=1, awvalid=1 or
wvalid=1 associated with a new transaction). The BUSY bits deassert as soon as the
outstanding transaction counters decrement to zero upon receiving a completed R or B channel
handshake of the last outstanding read/write transaction. If any further command transfers are
received on the SI after the BUSY bit is deasserted, the BUSY bit become asserted again until
all associated activity is again completed.
The BUSY bits are not masked while reads or writes remain in normal operating mode. While read or write traffic is blocked, deassertion of the BUSY bit indicates that the autonomous flushing operation of the firewall has completed for read or write. When read or write traffic is in normal operating mode, deassertion of the BUSY bit indicates that all outstanding transactions have completed normally. In either case, observing both the READ_RESPONSE_BUSY and WRITE_RESPONSE_BUSY low indicates that it is safe to reset all downstream (MI-side) devices and request unblocking of the firewall through the control interface (provided no new transactions arrive at the SI after BUSY deasserts).