MI-Side Interrupt Enable Register - MI-Side Interrupt Enable Register - 1.2 English - PG293

AXI Protocol Firewall IP LogiCORE IP Product Guide (PG293)
Document ID
PG293
Release Date
2025-08-29
Version
1.2 English

The MI-Side Interrupt Enable Register is shown in the following table.

Table 1. MI-Side Interrupt Enable Register (0x204)
Bit(s) Name Core Access Default Value Description
31   RW 0 Enable firewall blocking due to XILINX_WR_DECERR. 1
30   RW 0 Enable firewall blocking due to XILINX_WR_SLVERR. 1
29:25 Reserved RW   Reserved
24   RW 0 Enable interrupt for User-defined Write Block.
23   RW 0 Enable interrupt for XILINX_WR_DECERR events.
22   RW 0 Enable interrupt for XILINX_WR_DECERR events.
21:17   RW   Enable interrupt for corresponding fault in MI-side Fault Status Register Bits[21:17].
16 Reserved RW   Reserved (Always zero)
15   RW 0 Enable firewall blocking due to XILINX_RD_DECERR. 1
14   RW 0 Enable firewall blocking due to XILINX_RD_SLVERR. 1
13:9 Reserved RW   Reserved
8   RW 0 Enable interrupt for User-defined Read Block.
5:1   RW 0 Enable interrupt for corresponding fault in MI-side Fault Status Register Bits[5:1].
0 Reserved RW   Reserved (Always zero)
  1. When any of Bits[31:30, 15:14] are disabled (0), the corresponding error response event can be recorded in the MI-side Fault Status Register and can still issue an interrupt if the corresponding "Enable interrupt" bit is set, but will not cause the firewall to become blocked.