The MI-Side Fault Status register is shown in the following table.
| Bit(s) | Name | Core Access | Default Value | Description |
|---|---|---|---|---|
| 31:25 | Reserved | RO | All zeros | |
| 24 | User-defined Write Block | RO | 0 | This indicates a block resulting from writing and setting Bit[24] in the MI-Side Soft Fault Control Register. |
| 23 | XILINX_WR_DECERR | RO | 0 | |
| 22 | XILINX_WR_SLVERR | RO | 0 | |
| 21 | ERRS_BVALID_STABLE | RO | 0 | |
| 20 | ERRS_BRESP | RO | 0 | |
| 19 | RECS_WRITE_TO_BVALID_MAX_WAIT | RO | 0 | |
| 18 | RECS_WREADY_MAX_WAIT | RO | 0 | |
| 17 | RECS_AWREADY_MAX_WAIT | RO | 0 | |
| 16 | WRITE_RESPONSE_BUSY | RO | 0 | Indicates whether there are outstanding write transactions that still need to be completed on the SI; deasserts as soon as outstanding writes decrement to zero. (Not masked while writes are in normal operating mode.) |
| 15:9 | Reserved | RO | All zeros | |
| 8 | User-defined Read Block | RO | 0 | This indicates a block resulting from writing and setting Bit[8] in the MI-Side Soft Fault Control Register. |
| 7 | XILINX_RD_DECERR | RO | 0 | |
| 6 | XILINX_RD_SLVERR | RO | 0 | |
| 5 | ERRS_RVALID_STABLE | RO | 0 | |
| 4 | ERRS_RID | RO | 0 | |
| 3 | ERRS_RDATA_NUM | RO | 0 | |
| 2 | RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT | RO | 0 | |
| 1 | RECS_ARREADY_MAX_WAIT | RO | 0 | |
| 0 | READ_RESPONSE_BUSY | RO | 0 | Indicates whether there are outstanding read transactions that still need to be completed on the SI; deasserts as soon as outstanding reads decrements to zero. (Not masked while reads are in normal operating mode.) |