|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
Adaptive SoC, UltraScale+™, UltraScale, AMD Zynq™ 7000 SoC,
7 series FPGAs |
| Supported User Interfaces |
AXI4, AXI4-Lite, AXI3
|
| Resources |
N/A |
| Provided with
Core
|
| Design Files |
SystemVerilog |
| Example Design |
SystemVerilog |
| Test Bench |
N/A |
| Constraints File |
N/A |
| Simulation Model |
Unencrypted SystemVerilog |
| Supported S/W Driver |
N/A |
| Tested Design
Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 76037
|
| All Vivado IP Change Logs |
Master Vivado IP
Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|