The Device Global Interrupt Enable Register is shown in the following table.
| Bit(s) | Name | Core Access | Default Value | Description |
|---|---|---|---|---|
| 31:1 | Reserved | RW | Reserved | |
| 0 | Global Interrupt Enable | RW | 0 |
When FIREWALL_MODE = MI, asserts ip2intc_irpt output when any of the faults enabled by the MI-side Interrupt Enable Register are active. When FIREWALL_MODE = SI, asserts ip2intc_irpt output when any of the faults enabled by the SI-side Interrupt Enable Register are active. |