If ENABLE_CTL_CLOCK==0, all I/O
signals on the IP are synchronized to the aclk input.
If ENABLE_CTL_CLOCK==1, the aclk_ctl input port becomes enabled and used
by the S_AXI_CTL interface; other interfaces and I/O signals remain
controlled by aclk . All information
pathways spanning between the control registers and the remaining
Firewall logic (payload propagation and fault-checking) are treated
as asynchronous clock-domain crossings. Internally-generated
constraints automatically exclude these pathways from observed
timing paths. If the main aclk becomes
non-operational (stopped), read/write access to all control
registers remains available using aclk_ctl . However, any changes written to
control registers while aclk is stopped
do not take effect in the main Firewall logic until a few cycles
after aclk resumes clocking. For example, if a User-defined Block
or Soft Pause is requested while aclk is
stopped, some AXI transfers across the Firewall might still occur
for a few cycles after aclk resumes,
until the recent control information changes get
resynchronized.