The AXI Firewall IP is deployed in MI-side mode when a reliable upstream system accesses a downstream subsystem of questionable reliability. A common example is in hardware acceleration systems, in which user-defined acceleration kernels are loaded into a re-programmable region of the FPGA. Potentially fatal conditions that might arise in the user region must be prevented from blocking host access to the FPGA, typically through the PCIe® bridge, which must remain operational.
The AXI Firewall IP is deployed in SI-side mode when a reliable downstream system is accessed by an upstream subsystem of questionable reliability. A common example is in hardware acceleration systems, in which a user-defined acceleration kernel loaded into a re-programmable region of the FPGA acts as a master to access remote memory locations through the PCIe bridge. Potentially fatal conditions that might arise in the kernel must be prevented from corrupting PCIe traffic or the remote system.