Data Lane Mapping - TX - 3.0 English - PG292

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)
Document ID
PG292
Release Date
2025-12-05
Version
3.0 English

For transmit data tx_axis_tdata, the port is logically divided into lane 0 to lane 3 for the 32-bit interface, or lane 0 to lane 7 for the 64-bit interface with the corresponding bit of the tx_axis_tkeep word signifying valid data on tx_axis_tdata.

Table 1. tx_axis_tdata Lanes – 32-bits
Lane/ tx_axis_tkeep tx_axis_tdata[31:0]
0 7:0
1 15:8
2 23:16
3 31:24
Table 2. tx_axis_tdata Lanes – 64-bits
Lane/ tx_axis_tkeep tx_axis_tdata[63:0]
0 7:0
1 15:8
2 23:16
3 31:24
4 39:32
5 47:40
6 55:48
7 63:56