Port Descriptions - 2.0 English - PG290

SMPTE UHD-SDI Receiver Subsystem LogiCORE IP Product Guide (PG290)

Document ID: PG290
Release Date: 2024-12-11
Version: 2.0 English

Table 1. Port Descriptions
Signal Name	Interface	Type	Description
s_axi_aclk	Clock	Input	Input clock for AXI4-Lite Interface
s_axi_aresetn	reset	Input	Active-Low reset for AXI4-Lite Interface
s_axi_*	s_axi_ctrl		AXI4-Lite Interface
aud_mclk	Clock	Input	Input audio clock. Typically a multiple of Fs
m_axis_aud_aclk	Clock	Input	AXIS Audio streaming clock
m_axis_aud_resetn	Reset	Input	Active-Low AXIS audio reset
m_axis_aud_*	Audio AXIS Interface	Master	Master AXIS audio interface
s_axis_aud_*	Audio AXIS Interface	Slave	Slave AXIS audio interface
m_aud_pulse	Signal	Output	Pulse on aud_clk with sample frequency