Required Constraints
This section defines the additional constraint requirements for the subsystem. Constraints are provided with a Xilinx Design Constraints (XDC) file. An XDC is provided with the HDL example design to give a starting point for constraints for your design.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP subsystem.
Clock Frequencies
See Clocking.
Clock Management
The SMPTE UHD-SDI RX Subsystem generates the required clock constraints when generated using out-of-context mode with <component name>_ooc.xdc. You can use these or update as required for other clock constraints.
Clock Placement
This section is not applicable for this IP subsystem.
Banking
This section is not applicable for this IP subsystem.
Transceiver Placement
This section is not applicable for this IP subsystem.
I/O Standard and Placement
This section is not applicable for this IP subsystem.