Programming Sequence - 2.0 English - PG289

The SMPTE UHD-SDI Transmitter (TX) subsystem is delivered with a bare-metal driver and API designed to handle all programming of the subsystem core. This driver is automatically available in the AMD Vitis™ development platform when you create it from a .xsa file, which includes the UHD-SDI TX Subsystem. This bare-metal driver is also available from the AMD GitHub. The example designs in Example Design showcase the use of the drivers in an application.

Information on Linux drivers can be found on the AMD Wiki.

Line Insertion Procedure

Step 1 (Inside SDI TXSS IP)

1. IP receives user-inputted native data streams.
2. Inserts the ST352 payload on the data stream.
3. Sends the stream to the SDI_TX_ANC_DSC_OUT for ANC/Audio packet insertion.

Step 2 and 3 (Outside IP Core)

1. Inserts the ANC or Audio packets in the received SDI_TX_ANC_DSC_OUT stream from the SDI TX SS core.
2. Sends the updated DS stream to the SDI TX core via SDI_TX_ANC_DS_IN.

Step 4 (Inside SDI TXSS IP)

1. If enabled, inserts the line number into SDI_TX_ANC_DS_IN.
2. Calculates and inserts the CRC, and inserts the sync bit to the DS stream.
3. Performs the scrambling encoding and sends the stream to the SDI PHY via the M_AXIS_TX interface.