The following figure shows the UltraScale GT clocking architecture.
Two reference clocks are used to support integer and fractional line rates of SDI. The reference clock for QPLL0 is fixed to 297 MHz from the on-board Si570 chip. The reference clock for the CPLL is fixed at 296.7 MHz from Si5328 chip output. The CPLL switches between the 297 MHz and the 296.7 MHz reference clocks using the CPLLREFCLKSEL.
Therefore, it is not recommended to use this clocking configuration when both transmit and receive 12G-SDI integer and fractional modes use the same transceiver. If required, AMD recommends to use a CPLL-QPLL combination with CPLL for TX and QPLL0/1 for RX as shown in the previous figure.
You can select the integer and fractional TX rates using CPLL reference clock input selection with 297 MHz and 296.7 MHz, respectively. This CPLL/QPLL clocking combination is not feasible with -1 speed grade devices because CPLL does not support 12G-SDI line rates.
You need to select an AMD UltraScale+™ GTH/GTY -2 speed grade or faster rate with >0.85V. Refer to the respective FPGA data sheets for CPLL line rate limits. The UHD-SDI example designs are updated to use the CPLL and QPLL clocking combination. The UHD-SDI GT IP is updated to provide CPLL support from version 2019.2 or later.