AXI Multichannel Direct Memory Access LogiCORE IP Product Guide (PG288) - 1.2 English - PG288

Document ID: PG288
Release Date: 2024-11-13
Version: 1.2 English

Introduction
Features
IP Facts
Overview
Feature Summary
Applications
Licensing and Ordering
Product Specification
Performance
Maximum Frequencies
Latency and Throughput
Resource Utilization
Port Descriptions
Register Space
MM2S Common Control Register (0x000)
MM2S Common Status Register (0x004)
MM2S Channel Enable/Disable Register (0x008)
MM2S Channel In Progress Register (0x00C)
MM2S Error Register (0x010)
MM2S Channel Queue Scheduler Type (0x014)
MM2S Channel Weight Registers (0x018, 0x01C)
MM2S Channels Completed Registers (0x020)
MM2S ARCACHE and ARUSER Registers (0x024)
MM2S Channel Interrupt Monitor Register (0x028)
MM2S Channel Observer Group 1-6 (0x440–0x454)
Channel Control Register
Channel Status Register
Channel Current Descriptor Registers
Channel Tail Descriptor Register
Packets Processed Statistics
S2MM Common Control Register (0x500)
S2MM Common Status Register (0x504)
S2MM Channel Enable/Disable Register (0x508)
S2MM Channel In Progress Register (0x50C)
S2MM Error Register (0x510)
S2MM Packet Drop Status (0x514)
S2MM Channels Completed Register (0x518)
S2MM AWCACHE and AWUSER Register (0x51C)
S2MM Channel Interrupt Monitor Register (0x520)
S2MM Channel Observer Group 1-6 Registers (0x940–0x954)
Channel Control Register
Channel Status Register
Channel Current Descriptor Registers
Channel Tail Descriptor Register
Packet Drop Statistic
Packets Processed Statistics
SG Cache/User Register (0x4B0)
Scatter Gather Buffer Descriptor
Next Descriptor Pointer (0x00)
Next Descriptor MSB Pointer (0x04)
Buffer Address (0x08)
MSB Buffer Address MSB (0x0C)
Control (0x14)
Control Sideband (0x18)
Status (0x1C)
APP0–APP4 Fields (0x20–0x30)
Control (0x14)
Status (0x18)
Sideband Status (0x1C)
APP0–APP3 Fields (0x20–0x2C)
APP4 Field (0x30)
Descriptor Management
MM2S Descriptor Setting and AXI4-Stream Control Stream
S2MM Descriptor Setting and AXI Status Stream
Designing with the Core
Typical System Comprising AXI MCDMA
Clocking
Resets
Programming Sequence
Interrupts
Packet Drop on S2MM
Queue Scheduler in MM2S
Strict Priority Type of Scheduler
Weighted Round Robin (WRR)
Weighted Round Robin – Fair Distribution
Design Flow Steps
Customizing and Generating the Core
Basic Tab
Component Name
Enable Read Channel
Number of Channels
Memory Map Data Width
Stream Data Width
Max Burst Size
Queue Scheduler
Allow Unaligned Transfers
Enable Write Channel
Number of Channels
Memory Map Data Width
Stream Data Width
Max Burst Size
Allow Unaligned Transfers
Enable Asynchronous Clocks
Enable Control/Status Stream
Use RxLength in Status Stream
Width of Buffer Length Register
Disable Packet Drop
Enable Soft Reset Per Channel
Address Width (32 to 64)
Advanced Tab
Enable Single AXI4 Data Interface
Grouping MM2S and S2MM Channels
User Parameters
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Implementing the Example Design
Simulating the Example Design
Test Bench for the Example Design
Upgrading
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debug
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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