The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 05/16/2023 Version 1.1 | |
| IP Facts | Updated Resources URL in IP Facts table. |
| 05/11/2022 Version 1.1 | |
| Register Space | Updated the register description. |
| 08/09/2021 Version 1.1 | |
| General updates | Added support for AMD Versal™ example design in Table 1 |
| 02/04/2021 Version 1.1 | |
| General updates | Updated to support version 1.1 |
| 11/15/2019 Version 1.0 | |
| Synthesizable Example Design | Updated with the Vitis software platform flow. |
| 12/05/2018 Version 1.0 | |
| Register Space | Updated Bayer Phase register address from 0x0020 to 0x0028 |
| 04/04/2018 Version 1.0 | |
| General updates | Added option to use UltraRAM for line buffers on UltraScale+ devices. Added support for ZCU102, ZCU104, and ZCU106 boards in the synthesizable example design. |
| 10/04/2017 Version 1.0 | |
| General updates | Initial AMD release. |