This section contains information about constraining the core in the Vivado Design Suite.
Required Constraints
The only constraints required are clock frequency constraints for the core
clock, ap_clk. Paths from AXI4-Lite signals should be constrained with a set_false_path, causing setup and hold checks to be ignored for AXI4-Lite signals. These constraints are provided in the XDC
constraints file included with the core.