Y_U_V12_M16LE - Y_U_V12_M16LE - 3.1 English - PG278

Video Frame Buffer Read and Video Frame Buffer Write v3.1 LogiCORE IP Product Guide (PG278)

Document_ID
PG278
Release_Date
2026-07-22
Version
3.1 English

Three Planar YUV 4:4:4 with 12-bits per component, where each component is packed to 16-bits with MSB alignment. Y, U, and V are stored in three separate planes, as shown.

63:52 51:48 47:37 36:32 31:20 19:16 15:4 3:0
Y3 x Y2 x Y1 x Y0 x
63:52 51:48 47:37 36:32 31:20 19:16 15:4 3:0
U3 x U2 x U1 x U0 x
63:52 51:48 47:37 36:32 31:20 19:16 15:4 3:0
V3 x V2 x V1 x V0 x