Tile Format - Tile Format - 3.1 English - PG278

Video Frame Buffer Read and Video Frame Buffer Write v3.1 LogiCORE IP Product Guide (PG278)

Document_ID
PG278
Release_Date
2026-07-22
Version
3.1 English

Tiling is a method of re-arranging the pixels of a surface so that pixels that are close in the two-dimensional euclidean space are more likely to be stored close to each other in the memory. A tiled image is formed by dividing the image pixels into two-dimensional blocks or tiles. Each tile takes up a chunk of contiguous memory. Tiles are stored in raster scan order from left to right and from top to bottom within each plane.

Tile0 Tile1 Tile2 ... TileN-2 TileN-1  
TileN TileN+1 TileN+2 ... Tile2N-2 Tile2N-1
Tile2N Tile2N+1 Tile2N+2 ... Tile3N-2 Tile3N-1
... ... ... ... ... ...
Note: Tile Format is supported only in the AMD Versal™ AI Edge Series Gen 2 and AMD Versal™ Prime Series Gen 2 devices where Video Codec Unit (VCU2) AMD LogiCORE™ is available as a Hard IP. For more information, refer to the Versal AI Edge Gen 2 H.264/H.265/JPEG Video Codec Unit 2 Solutions LogiCORE IP Product Guide (PG447).

The frame buffer read and write IPs support memory video format in two tile sizes: 32 × 4 and 64 × 4.

32 × 4 Tiled Format

With B corresponding to a block of 4 × 4 pixel components, the sample order within a 32 × 4 tile corresponds to a sequence of eight 4 × 4 blocks:

B0 B1 B2 B3 B4 B5 B6 B7
64 × 4 Tiled Format

The sample order within a 64 × 4 tile corresponds to a sequence of sixteen 4 × 4 blocks:

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15

The sample order within each 4 × 4 block B corresponds to the raster scan order.

Luma

The order of pixel components within a 4 × 4 block in luma plane is shown below:

Yx,0 Yx,1 Yx,2 Yx,3
Yx,4 Yx,5 Yx,6 Yx,7
Yx,8 Yx,9 Yx,A Yx,B
Yx,C Yx,D Yx,E Yx,F
Chroma Non-Interleaved

With C corresponding to either Cb or Cr block, the order of pixel components within a 4 × 4 block in Cb or Cr plane is shown below:

Cx,0 Cx,1 Cx,2 Cx,3
Cx,4 Cx,5 Cx,6 Cx,7
Cx,8 Cx,9 Cx,A Cx,B
Cx,C Cx,D Cx,E Cx,F
Chroma Interleaved

The order of pixel components within a 4 × 4 block in interleaved Chroma plane is shown below:

Cbx,0 Crx,0 Cbx,1 Crx,1
Cbx,2 Crx,2 Cbx,3 Crx,3
Cbx,4 Crx,4 Cbx,5 Crx,5
Cbx,6 Crx,6 Cbx,7 Crx,7

Consequently, in a 4:2:0 picture, there are half as many chroma tiles as luma tiles because the chroma plane has half the vertical size of the luma plane besides having the same horizontal size, as Cb and Cr components are interleaved. In 4:4:4 and 4:2:2 pictures, there are equal number of chroma and luma tiles. The 4:0:0 monochrome picture consists of only luma tiles.

The pixel components within each tile are fully packed so the memory footprint of a tile is:

  • 128 bytes for an 8-bit 32 × 4 tile
  • 160 bytes for a 10-bit 32 × 4 tile
  • 192 bytes for a 12-bit 32 × 4 tile
  • 256 bytes for an 8-bit 64 × 4 tile
  • 320 bytes for a 10-bit 64 × 4 tile
  • 384 bytes for a 12-bit 64 × 4 tile

The following tables explain the expected pixel mappings in memory for each of the supported tile formats.

8-bit Tile Format
8-bit samples are packed starting from the least significant bits of memory words. The footprint of an 8-bit 32x4 tile is 128 bytes (8 x 128-bit words) and the footprint of an 8-bit 64x4 tile is 256 bytes (16 x 128-bit words). An example of tile buffer for luma samples is as follows:
10-bit Tile Format
10-bit samples are packed starting from the least significant bits of memory words. The footprint of a 10-bit 32x4 tile is 160 bytes (10 x 128-bit words) and the footprint of a 10-bit 64x4 tile is 320 bytes (20 x 128-bit words). An example of tile buffer for luma samples is as follows:
12-bit Tile Format
12-bit samples are packed starting from the least significant bits of memory words. The footprint of a 12-bit 32x4 tile is 192 bytes (12 x 128-bit words) and the footprint of a 12-bit 64x4 tile is 384 bytes (24 x 128-bit words). An example of tile buffer for luma samples is as follows:

The Video Frame Buffer Read and Video Frame Buffer Write support the pixel formats with tile scan order in memory as described in the following table.

Table 1. Pixel Formats with Tile Scan Order
Video Format Description Bits per Component Bytes per 32x4 Tile Bytes per 64x4 Tile
Y_U_V8 3 planar YUV 4:4:4 8 128 256
Y_U_V10 3 planar YUV 4:4:4 10 160 320
Y_U_V12 3 planar YUV 4:4:4 12 192 384
Y_UV8 semi-planar YUV 4:2:2 8 128 256
Y_UV10 semi-planar YUV 4:2:2 10 160 320
Y_UV12 semi-planar YUV 4:2:2 12 192 384
Y_UV8_420 semi-planar YUV 4:2:0 8 128 256
Y_UV10_420 semi-planar YUV 4:2:0 10 160 320
Y_UV12_420 semi-planar YUV 4:2:0 12 192 384
Y8 monochrome YUV 4:0:0 8 128 256
Y10 monochrome YUV 4:0:0 10 160 320
Y12 monochrome YUV 4:0:0 12 192 384

The following table shows the IP format to common video pixel format for tile mode.

Table 2. IP Format to Common Video Pixel Format for Tile Format
IP Format V4L2 4CC DRM 4CC
Y8 V4L2_PIX_FMT_T5M8 DRM_FORMAT_T5M8
Y8 V4L2_PIX_FMT_T6M8 DRM_FORMAT_T6M8
Y10 V4L2_PIX_FMT_T5MA DRM_FORMAT_T5MA
Y10 V4L2_PIX_FMT_T6MA DRM_FORMAT_T6MA
Y12 V4L2_PIX_FMT_T5MC DRM_FORMAT_T5MC
Y12 V4L2_PIX_FMT_T6MC DRM_FORMAT_T6MC
Y_UV8_420 V4L2_PIX_FMT_T508 DRM_FORMAT_T508
Y_UV8_420 V4L2_PIX_FMT_T608 DRM_FORMAT_T608
Y_UV10_420 V4L2_PIX_FMT_T50A DRM_FORMAT_T50A
Y_UV10_420 V4L2_PIX_FMT_T60A DRM_FORMAT_T60A
Y_UV12_420 V4L2_PIX_FMT_T50C DRM_FORMAT_T50C
Y_UV12_420 V4L2_PIX_FMT_T60C DRM_FORMAT_T60C
Y_UV8 V4L2_PIX_FMT_T528 DRM_FORMAT_T528
Y_UV8 V4L2_PIX_FMT_T628 DRM_FORMAT_T628
Y_UV10 V4L2_PIX_FMT_T52A DRM_FORMAT_T52A
Y_UV10 V4L2_PIX_FMT_T62A DRM_FORMAT_T62A
Y_UV12 V4L2_PIX_FMT_T52C DRM_FORMAT_T52C
Y_UV12 V4L2_PIX_FMT_T62C DRM_FORMAT_T62C
Y_U_V8 V4L2_PIX_FMT_T548 DRM_FORMAT_T548
Y_U_V8 V4L2_PIX_FMT_T648 DRM_FORMAT_T648
Y_U_V10 V4L2_PIX_FMT_T54A DRM_FORMAT_T54A
Y_U_V10 V4L2_PIX_FMT_T64A DRM_FORMAT_T64A
Y_U_V12 V4L2_PIX_FMT_T54C DRM_FORMAT_T54C
Y_U_V12 V4L2_PIX_FMT_T64C DRM_FORMAT_T64C