Revision History - Revision History - 3.1 English - PG278

Video Frame Buffer Read and Video Frame Buffer Write v3.1 LogiCORE IP Product Guide (PG278)
Document_ID
PG278
Release_Date
2026-07-22
Version
3.1 English

The following table shows the revision history for this document.

Section Revision Summary
07/22/2026 Version 3.1
Features Updated descriptions.
IP Facts Updated tile mode description in Supported Device Family.
Feature Summary Added RGBA.
Performance Added Spartan UltraScale+.
Common Interface Signals Updated table descriptions.
sync_eol, sync_eof, and partial_frm_wr_done Added sections.
Memory Mapped AXI4 Interface Updated and added ID 45-60 descriptions to Pixel Formats with Raster Scan Order table. Updated IP Format to Common Video Pixel Format table.
Y_U_V10_L16LE to Y12_M16LE Added tables.
Tile Format Added IP Format to Common Video Pixel Format for Tile Format table.
Top-Level Registers Added 0x0070.
Stride (0x0020) Register Added 1024 and 8, 16 in stride value description.
Memory Video Format (0x0028) Register Updated Compatible Memory and Streaming Video Formats table.
Plane1 Buffer (0x0030), Plane 2 Buffer (0x003C), and Plane3 Buffer (0x0054) Updated description.
Line Count (0x0070) Register Added new section.
Interface Updated figures.
General Settings Added Enable Partial Frame Write Done Signal and updated Video Formats list.
User Parameters Updated table.
Example Design Added SCU200 row.
Running the Example Design Updated directory lines.
Vitis Software Platform Workflow Updated figures.
Changes from v3.0 to v3.1 Added section.
11/20/2025 Version 3.0
Tile Format Updated the section.
Stride (0x0020) Register Updated the section.
Interface Updated the section.
General Settings Updated the section.
User Parameters Updated the section.
Example Design Added SCU200 to table.
Running the Example Design Updated the section.
Prerequisites Updated the section.
05/29/2025 Version 3.0
Entire document
  • Elaborated the description of Tile formats.
  • Added URAM support for line buffers.
  • Updated Vitis application flow as per Vitis Unified IDE.
12/11/2024 Version 3.0
Entire Document Added Y12, Y_UV12, Y_UV12_420, Y_U_V12, YUV_444 3 planar 12-bit video formats, tile format, and alpha formats in frame buffer write
11/19/2023 Version 2.5
Entire Document Added Y_U_V8_420 and Y_U_V8 video formats where applicable
04/12/2023 Version 2.4
IP Facts Updated the PRU links.
05/11/2022 Version 2.4
Product Specification Added Y_U_V10.
User Parameters Updated the table.
Upgrading in the Vivado Design Suite Updated the section.
10/27/2021 Version 2.3
N/A
  • Added support for 16K resolution and 3 Planar video format
  • Updated enhancement for field ID signal
08/09/2021
Example Design Added support for AMD Versal™ example design.
02/04/2021 Version 2.2
Vitis Software Platform Workflow Updated for v2.2.
07/08/2020 Version 2.1
N/A
  • Updated AXI-Stream Video Interface section in Chapter 2.
  • Updated Control (0x0000) Register in Chapter 2.
  • Updated Stride (0x0020) Register in Chapter 2.
  • Updated Plane1 Buffer (0x0030) and Plane 2 Buffer (0x003C) Registers in Chapter 2.
  • Updated Samples Per Clock description in Chapter 4.
12/19/2019 Version 2.1
Design Flow Steps Vitis flow updated.
11/14/2018 Version 2.1
Features Added support for 8K30.
fid error Updated the UG934 link.
Memory Mapped AXI4 Interface Added Table 2.
Table 2 Updated UG934 link in Note.
N/A Fixed AR 68764 link.
04/04/2018 Version 2.0
N/A
  • Added support for interlaced video
  • Added BGR8 video format
  • Added support for ZCU102, ZCU104, and ZCU106 boards in the example design.
10/04/2017 Version 2.0
N/A Added new video formats, added second buffer for semi-planar formats, added support for 64-bit addressing on memory interfaces.
04/05/2017 Version 1.0
N/A Initial AMD release.